What is make modules in linux

Linux ‘make’ Command Explained With Examples

The make command in Linux is one of the most frequently used commands by the system administrators and the programmers. While it helps administrators in compiling and installing many open source utilities through the command line, programmers use it to manage the compilation of their large and complicated projects. In this article, we will discuss the internal working of the make command along with some practical examples.

How make Command Works

For those who are unaware, the make command accepts targets as command line arguments. These targets are usually specified in a file named ‘Makefile’, which also contains the associated action corresponding to the targets. For more information, read our series of articles on how Makefiles work.

When the make command is executed for the very first time, it scans the Makefile to find the target (supplied to it) and then reads its dependencies. If these dependencies are targets themselves, it scans the Makefile for these targets and builds their dependencies (if any), and then builds them. Once the main dependencies are build, it then builds the main target (that was passed to the make command).

Now, suppose you make change to only one source file and you execute the make command again, it will only compile the object files corresponding to that source file, and hence will save a lot of time in compiling the final executable.

make Command Examples

Here are the details of the testing environment used for this article :

• OS – Ubuntu 13.04
• Shell – Bash 4.2.45
• Application – GNU Make 3.81

Following are the contents of the project :

and here are the contents of the Makefile :

Now, let’s have a look at some of the examples of make command usage in Linux.

1) A simple example

To compile the project, you can either simply use ‘make’ or can use the target ‘all’ with the make command.

So you can see that the make command first creates the dependencies and then the actual target.

If you take a look at the directory contents, there would be .o files and executable files in it :

Now, suppose you make some change in test.c and re-compile the project with make :

So you can see that only test.o is recompiled, while anotherTest.o is not recompiled.

Now, to clean all the object files along with the ‘test’ executable, you can use the target ‘clean’ :

So you can see that all the .o files and the executable ‘test’ were deleted.

2) Always make all the targets through -B option

By now, you’d probably be aware that the make command does not compile those files that have not changed since last time. But, if you want to override the make’s default behavior, you can use the -B option.

Here is an example :

So you can see that while ‘make’ command did not compile any file, ‘make -B’ forcibly compiled all the objects along with the final executable.

3) Print debugging information using -d option

If you want a detailed account of what the make command actually does when it is executed, use the -d option.

Here is an example :

It’s a long output. You can see that I used the more command to view the output page by page. You have to see it for yourself to get a better idea of the details this option is capable to produce.

4) Change the directory using -C option

You can provide a different directory path to the make command, which it would switch to before looking for a Makefile.

Here is an example. Suppose you are currently in this directory :

But you want to run make with the Makefile kept at ../make-dir/. So here is what you’ve to do :

So you can see that the make command switched to the specified directory, executed there and then switched back.

5) Treat any other file as ‘Makefile’ through -f option

If you want to rename your Makefile to let’s say ‘my_makefile’ or any other name, and want the make command to treat it like the default ‘Makefile’, you can use the -f option for this.

Here is an example :

This way the make command will pick and scan my_makefile instead of Makefile.

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Linux make command

On Unix-like operating systems, make is a utility for building and maintaining groups of programs (and other types of files) from source code.

This page covers the GNU/Linux version of make.

Description

The purpose of the make utility is to determine automatically which pieces of a large program need to be re-compiled, and issue the commands necessary to recompile them. This documentation describes the GNU implementation of make, which was written by Richard Stallman and Roland McGrath, and is currently maintained by Paul Smith. Many of the examples listed below show C programs, since they are most common, but you can use make with any programming language whose compiler can be run with a shell command. In fact, make is not limited to programs. You can use it to describe any task where some files must be updated automatically from others whenever the others change.

To prepare to use make, you must write a file called the makefile that describes the relationships among files in your program, and the states the commands for updating each file. In a program, typically the executable file is updated from object files, which are in turn made by compiling source files.

Once a suitable makefile exists, each time you change some source files, this simple shell command:

suffices to perform all necessary recompilations. The make program uses the makefile data base and the last-modification times of the files to decide which of the files need to be updated. For each of those files, it issues the commands recorded in the database.

make executes commands in the makefile to update one or more target names, where name is typically a program. If no -f option is present, make will look for the makefiles GNUmakefile, makefile, and Makefile, in that order.

Normally you should call your makefile either makefile or Makefile. (The officially recommended name is Makefile because it appears prominently near the beginning of a directory listing, right near other important files such as README.) The first name checked, GNUmakefile, is not recommended for most makefiles. You should use this name if you have a makefile that is specific to GNU make, and will not be understood by other versions of make. If makefile is a dash («—«), the standard input is read.

make updates a target if it depends on prerequisite files that have been modified since the target was last modified, or if the target does not exist.

Syntax

Options

-b, -m	These options are ignored, but included for compatibility with other versions of make.
-B, —always-make	Unconditionally make all targets.
-C dir, —directory=dir	Change to directory dir before reading the makefiles or doing anything else. If multiple -C options are specified, each is interpreted relative to the previous one: -C / -C etc is equivalent to -C /etc. This is typically used with recursive invocations of make.
-d	Print debugging information in addition to normal processing. The debugging information says which files are being considered for remaking, which file-times are being compared and with what results, which files actually need to be remade, which implicit rules are considered and that are applied; everything interesting about how make decides what to do.
—debug[=FLAGS]	Print debugging information in addition to normal processing. If the FLAGS are omitted, then the behavior is the same as if -d was specified. FLAGS may be a for all debugging output (same as using -d), b for basic debugging, v for more verbose basic debugging, i for showing implicit rules, j for details on invocation of commands, and m for debugging while remaking makefiles.
-e, —environment-overrides	Give variables taken from the environment precedence over variables from makefiles.
-f file, —file=file, —makefile=file	Use file as a makefile.
-i, —ignore-errors	Ignore all errors in commands executed to remake files.
-I dir, —include-dir=dir	Specifies a directory dir to search for included makefiles. If several -I options are used to specify several directories, the directories are searched in the order specified. Unlike the arguments to other flags of make, directories given with -I flags may come directly after the flag: -Idir is allowed, as well as -I dir. This syntax is allowed for compatibility with the C preprocessor’s -I flag.
-j [jobs], —jobs[=jobs]	Specifies the number of jobs (commands) to run simultaneously. If there is more than one -j option, the last one is effective. If the -j option is given without an argument, make will not limit the number of jobs that can run simultaneously.
-k, —keep-going	Continue as much as possible after an error. While the target that failed (and those that depend on it) cannot be remade, the other dependencies of these targets can be processed all the same.
-l [load], —load-average[=load]	Specifies that no new jobs (commands) should be started if there are others jobs running and the load average is at least load (a floating-point number). With no argument, removes a previous load limit.
-L, —check-symlink-times	Use whichever is the latest modification time between symlinks and target.
-n, —just-print, —dry-run, —recon	Print the commands that would be executed, but do not execute them.
-o file, —old-file=file, —assume-old=file	Do not remake the file file even if it is older than its dependencies, and do not remake anything on account of changes in file. Essentially the file is treated as very old and its rules are ignored.
-p, —print-data-base	Print the database (rules and variable values) that results from reading the makefiles; then execute as usual or as otherwise specified. This also prints the version information given by the -v switch (see below). To print the database without trying to remake any files, use make -p -f/dev/null.
-q, —question	«Question mode.» Do not run any commands, or print anything; just return an exit status that is zero if the specified targets are already up to date, nonzero otherwise.
-r, —no-builtin-rules	Eliminate use of the built-in implicit rules. Also, clear out the default list of suffixes for suffix rules.
-R, —no-builtin-variables	Don’t define any built-in variables.
-s, —silent, —quiet	Silent operation; do not print the commands as they are executed.
-S, —no-keep-going, —stop	Cancel the effect of the -k option. This is never necessary except in a recursive make where -k might be inherited from the top-level make via MAKEFLAGS or if you set -k in MAKEFLAGS in your environment.
-t, —touch	Touch files (mark them up to date without really changing them) instead of running their commands. This is used to pretend that the commands were done, to fool future invocations of make.
-v, —version	Print the version of make; also a Copyright, a list of authors and a notice that there is no warranty.
-w, —print-directory	Print a message containing the working directory before and after other processing. This may be useful for tracking down errors from complicated nests of recursive make commands.
—no-print-directory	Turn off -w, even if it was turned on implicitly.
-W file, —what-if=file, —new-file=file, —assume-new=file	Pretend that the target file has just been modified. When used with the -n flag, this shows you what would happen if you were to modify that file. Without -n, it is almost the same as running a touch command on the given file before running make, except that the modification time is changed only internally within make.
—warn-undefined-variables	Warn when an undefined variable is referenced.

Typical Use

make is typically used to build executable programs and libraries from source code. Generally speaking, make is applicable to any process that involves executing arbitrary commands to transform a source file to a target result. For example, make could be used to detect a change made to an image file (the source) and the transformation actions might be to convert the file to some specific format, copy the result into a content management system, and then send e-mail to a predefined set of users that the above actions were performed.

make is invoked with a list of target file names to build as command-line arguments:

Without arguments, make builds the first target that appears in its makefile, which is traditionally a target named all.

make decides whether a target needs to be regenerated by comparing file modification times. This solves the problem of avoiding the building of files that are already up to date, but it fails when a file changes but its modification time stays in the past. Such changes could be caused by restoring an older version of a source file, or when a network filesystem is a source of files and its clock or timezone is not synchronized with the machine running make. The user must handle this situation by forcing a complete build. Conversely, if a source file’s modification time is in the future, it may trigger unnecessary rebuilding.

Makefiles

make searches the current directory for the makefile to use. GNU make searches files for a file named one of GNUmakefile, makefile, and then Makefile, and runs the specified target(s) from that file.

The makefile language is similar to declarative programming, in which necessary end conditions are described but the order in which actions are to be taken is not important. This may be confusing to programmers used to imperative programming, which explicitly describes how the end result will be reached.

One problem in build automation is the tailoring of a build process to a given platform. For instance, the compiler used on one platform might not accept the same options as the one used on another. This is not well handled by make on its own. This problem is typically handled by generating separate platform-specific build instructions, which in turn may be processed by make. Common tools for this process are autoconf and cmake.

Rules

A makefile essentially consists of rules. Each rule begins with a dependency line which defines a target followed by a colon («:«) and optionally an enumeration of components (files or other targets) on which the target depends. The dependency line is arranged so that the target (left hand of the colon) depends on components (right hand of the colon). It is common to refer to components as prerequisites of the target.

Here, is the tab character. Usually each rule has a single unique target, rather than multiple targets.

For example, a C .o object file is created from .c files, so .c files come first (i.e. specific object file target depends on a C source file and header files). Because make itself does not understand, recognize or distinguish different kinds of files, this opens up the possibility for human error. A forgotten or an extra dependency may not be immediately obvious and may result in subtle bugs in the generated software. It is possible to write makefiles which generate these dependencies by calling third-party tools, and some makefile generators, such as the GNU automake toolchain, can do so automatically.

After each dependency line, a series of command lines may follow which define how to transform the components (usually source files) into the target (usually the «output»). If any of the components have been modified, the command lines are run.

With GNU make, the first command may appear on the same line after the prerequisites, separated by a semicolon:

Each command line must begin with a tab character to be recognized as a command. The tab is a whitespace character, but the space character does not have the same special meaning. This is problematic, since there may be no visual difference between a tab and a series of space characters. This aspect of the syntax of makefiles is often subject to criticism, and is important to take note.

However, GNU make (since version 3.82) allows the user to choose any symbol (one character) as the recipe prefix using the .RECIPEPREFIX special variable, for example:

Each command is executed by a separate shell or command-line interpreter instance. Since operating systems use different command-line interpreters this can lead to unportable makefiles. For instance, GNU make by default executes commands with /bin/sh, which is the shell where Unix commands like cp are normally used.

A rule may have no command lines defined. The dependency line can consist solely of components that refer to targets, for example:

The command lines of a rule are usually arranged so that they generate the target. An example: if «file.html» is newer, it is converted to text. The contents of the makefile:

The above rule would be triggered when make updates «file.txt«.

In the following invocation, make would typically use this rule to update the «file.txt» target if «file.html» were newer:

Command lines can have one or more of the following three prefixes:

• a hyphen-minus (—), specifying that errors are ignored
• an at sign (@), specifying that the command is not printed to standard output before it is executed
• a plus sign (+), the command is executed even if make is invoked in a «do not execute» mode

Ignoring errors and silencing all echo output can also be obtained via the special targets «.IGNORE» and «.SILENT«, respectively.

Macros

A makefile can contain definitions of macros. Macros are usually referred to as variables when they hold simple string definitions, like «CC=clang«, which would specify clang as the C compiler. Macros in makefiles may be overridden in the command-line arguments passed to the make utility. environment variables are also available as macros.

Macros allow users to specify the programs invoked and other custom behavior during the build process. For example, as just shown, the macro «CC» is frequently used in makefiles to refer to the location of a C compiler.

New macros are traditionally defined using capital letters:

A macro is used by expanding it. Traditionally this is done by enclosing its name inside $(). An equivalent form uses curly braces rather than parenthesis, i.e. $<>, which is the style used in BSD operating systems.

Macros can be composed of shell commands using the command substitution operator, denoted by backticks («` `«).

The content of the definition is stored «as is». Lazy evaluation is used, meaning that macros are normally expanded only when their expansions are actually required, such as when used in the command lines of a rule. For example:

The generic syntax for overriding macros on the command line is:

Makefiles can access any of a number of predefined internal macros, with «?» and «@» being the most common.

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